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Optimizing Quantum Error-Correction Protocols with Erasure Qubits

Shouzhen Gu1,2,*,†, Yotam Vaknin3,4,*, Alex Retzker3,4, and Aleksander Kubica3,1,2

  • *These authors contributed equally to this work.
  • †Contact author: shouzhen.gu@yale.edu
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PRX Quantum 6, 040354 – Published 4 December, 2025

DOI: https://doi.org/10.1103/985g-58gd

Abstract

Erasure qubits offer a promising avenue toward reducing the overhead of quantum error correction (QEC) protocols. However, they require additional operations, such as erasure checks, that may add extra noise and increase the run-time of QEC protocols. To assess the benefits provided by erasure qubits, we focus on the performance of the surface code as a quantum memory. In particular, we analyze various erasure check schedules, find the correctable regions in the phase space of error parameters, and probe the subthreshold scaling of the logical error rate. We then consider a realization of erasure qubits in the superconducting hardware architectures via dual-rail qubits. We use the standard transmon-based implementation of the surface code as the performance benchmark. Our results indicate that QEC protocols with erasure qubits can outperform the ones with state-of-the-art transmons, even in the absence of precise information about the locations of erasure errors.

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Physics Subject Headings (PhySH)

Popular Summary

Operating a quantum computer requires protecting the stored information from various sources of errors, for example, by redundantly encoding the qubits in an error-correcting code. Recently, there has been much interest in erasure qubits, where the most likely errors erase the computational information. In contrast with unknown errors, erasures are easier to handle, as they can be detected. In our work, we study the costs and benefits of using erasure qubits. Frequently checking for erasures gives more information about the locations of errors, but running these erasure checks takes time, during which more errors can accumulate on the device. We determine how often erasure checks should be performed in various scenarios. In addition, we consider different realizations of erasure qubits and analyze under what conditions they show an advantage.

In our study, we focus on the surface code as a quantum memory and evaluate three different frequencies of erasure checks during the error-correction protocol. For each erasure check schedule, we determine the maximum tolerable error rates through numerical simulation, allowing us to determine the best schedule to use. These results can be translated to analyze specific hardware realizations. The main conclusion is that erasure qubits win over standard qubits when erasure check times are short compared with the whole quantum error correction cycle, because proportionally fewer errors will accumulate during these checks.

The frequency of erasure checks is an important consideration when one is realistically evaluating the performance of erasure qubits. Additional optimizations would further cement erasure qubits as a practical way of protecting quantum information.

See Also

Surface Code with Imperfect Erasure Checks

Kathleen Chang, Shraddha Singh, Jahan Claes, Kaavya Sahay, James Teoh, and Shruti Puri
PRX Quantum 6, 040355 (2025)

Article Text

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Outline

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PRX Quantum 6, 040354– Published 4 December, 2025
  • Received 26 August 2024
  • Revised 26 August 2025
  • Accepted 22 October 2025
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Published by the American Physical Society under the terms of the Creative Commons Attribution 4.0 International license. Further distribution of this work must maintain attribution to the author(s) and the published article's title, journal citation, and DOI.

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