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Hybrid Cat-Transmon Architecture for Scalable, Hardware-Efficient Quantum Error Correction

Connor T. Hann1,*, Kyungjoo Noh1, Harald Putterman1, Matthew H. Matheny1, Joseph K. Iverson1, Michael T. Fang1, Christopher Chamberland1,†, Oskar Painter1,2,3, and Fernando G.S.L. Brandão1,2,‡

  • *Contact author: connohan@amazon.com
  • †Current affiliation: NVIDIA.
  • ‡Contact author: fbrandao@amazon.com
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PRX Quantum 6, 030305 – Published 11 July, 2025

DOI: https://doi.org/10.1103/75x7-5ysv

Abstract

Dissipative cat qubits are a promising physical platform for quantum computing, since their large noise bias can enable more hardware-efficient quantum error correction. In this work we theoretically study the long-term prospects of a hybrid cat-transmon quantum computing architecture where dissipative cat qubits play the role of data qubits, and error syndromes are measured using ancillary transmon qubits. The cat qubits’ noise bias enables more hardware-efficient quantum error correction, and the use of transmons allows for practical, high-fidelity syndrome measurement. While correction of the dominant cat Z errors with a repetition code has recently been demonstrated in experiment, here we show how the architecture can be scaled beyond a repetition code. In particular, we propose a cat-transmon entangling gate that enables the correction of residual cat X errors in a thin rectangular surface code, so that logical error can be arbitrarily suppressed by increasing code distance. We numerically estimate logical memory performance, finding significant overhead reductions in comparison to architectures without biased noise. For example, with current state-of-the-art coherence, physical error rates of 10−3 and noise biases in the range 103–104 are achievable. With this level of performance, the qubit overhead required to reach algorithmically relevant logical error rates with the cat-transmon architecture matches that of an unbiased-noise architecture with physical error rates in the range 10−5–10−4.

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Physics Subject Headings (PhySH)

Popular Summary

Quantum error correction (QEC) allows us to build reliable logical qubits out of noisy, error-prone physical qubits. The overhead cost of QEC can be prohibitive, however, with many physical qubits typically required to construct a single logical qubit. To address this challenge, we consider a more efficient approach to QEC based on so-called biased-noise cat qubits. While prior proposals have shown how cat qubits can be used to improve the efficiency of QEC in principle, onerous experimental requirements have made it difficult to realize these benefits in practice. Here, we present a novel cat-qubit architecture that relies only on well-established experimental capabilities, and we predict significant QEC efficiency improvements are already possible in current state-of-the-art experiments with this architecture.

The key feature of our architecture is the use of superconducting transmon qubits to measure the cats’ error syndromes. We show that easy-to-engineer cat-transmon interactions allow for fast, highly reliable error syndrome measurements. There is a price to pay for these practical benefits—the cats’ noise bias is limited by the transmons—but we show how all cat errors can ultimately be corrected regardless. Our cat-transmon approach to QEC is thus fully scalable, and we project significant QEC efficiency improvements at algorithmically relevant logical error rates.

Natural directions for future work include additional optimizations of the architecture’s hardware and gates, analysis of fault-tolerant logical operations, and further experimental demonstrations of the architecture’s key components.

Article Text

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PRX Quantum 6, 030305– Published 11 July, 2025
  • Received 22 November 2024
  • Revised 1 March 2025
  • Accepted 22 May 2025
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