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    Simulating quantum circuits with tree tensor networks using density-matrix renormalization group algorithm

    Aditya Dubey1,2,*, Zeki Zeybek2,3,†, and Peter Schmelcher2,3,‡

    • *Contact author: f20200627@goa.bits-pilani.ac.in
    • †Contact author: zeki.zeybek@uni-hamburg.de
    • ‡Contact author: peter.schmelcher@uni-hamburg.de

    Phys. Rev. B 112, 104312 – Published 15 September, 2025

    DOI: https://doi.org/10.1103/64hd-q4z5

    Abstract

    Quantum computing offers the potential for computational abilities that can go beyond classical machines. However, they are still limited by several challenges such as noise, decoherence, and gate errors. As a result, efficient classical simulation of quantum circuits is vital not only for validating and benchmarking quantum hardware but also for gaining deeper insights into the behavior of quantum algorithms. A promising framework for classical simulation is provided by tensor networks. Recently, the density-matrix renormalization group (DMRG) algorithm was developed for simulating quantum circuits using matrix product states (MPS). Although MPS are efficient for representing quantum states with one-dimensional correlation structures, the fixed linear geometry restricts the expressive power of the MPS. In this work, we extend the DMRG algorithm for simulating quantum circuits to tree tensor networks (TTNs). The framework employs a variational compression scheme that optimizes the TTN to approximate the evolved quantum state. To benchmark the method, we simulate random circuits and the quantum approximate optimization algorithm (QAOA) with various two-qubit gate connectivities. For the random circuits, we devise treelike gate layouts that are suitable for TTN and show that TTN requires less memory than MPS for the simulations. For the QAOA circuits, a naive TTN construction that exploits graph structure significantly improves the simulation fidelities. Our findings show that the DMRG algorithm with TTNs provides a promising framework for simulating quantum circuits, particularly when gate connectivities exhibit clustering or a hierarchical structure.

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