Scaling behavior in a sub-5-nm n-type monolayer transistor
Phys. Rev. Applied 25, 024078 – Published 25 February, 2026
DOI: https://doi.org/10.1103/r23v-kgmw
Abstract
Two-dimensional (2D) exhibits excellent interface compatibility with substrates, which makes it a promising channel material for field-effect transistors beyond the silicon-based era. A recent study has indicated the viability of the exfoliation of 2D to monolayer (ML) thickness utilizing liquid-phase methodologies assisted by sonication. This study applies ab initio quantum transport simulations to investigate the device performance limits of sub-5-nm ML metal-oxide-semiconductor field-effect transistors (MOSFETs). The on-state current, subthreshold swing, switching speed, and power consumption of n- and p-type ML MOSFETs in both the zigzag and armchair orientations are explored. No significant anisotropy is observed. Along the zigzag and armchair directions, the optimized n-type transistors can well satisfy the key criteria of the International Technology Roadmap for Semiconductors for high-performance applications at a 3-nm gate length, and for low-power applications at a 5-nm gate length. The performance of the n-type transistor exceeds that of the p-type one. The ML MOSFETs along the zigzag and armchair directions with gate length of 5 nm possess on-state current levels reaching up to 2452 and 1917 µA/µm, accompanied by corresponding energy-delay products and Js/µm, respectively, surpassing many other 2D MOSFETs. Our work demonstrates that ML as a channel candidate can help push Moore’s law down to the sub-5-nm regime.