Monolayer ( = C, Si, Ge): Enabling sub-5-nm MOSFETs compatible with silicon-based manufacturing
Phys. Rev. Applied 25, 014058 – Published 23 January, 2026
DOI: https://doi.org/10.1103/pp8h-r8wk
Abstract
Two-dimensional (2D) materials, with their atomic-scale thickness and high carrier mobility, are promising candidates for replacing silicon channels, offering significant potential for gate lengths below 5 nm. Monolayer ( = ) materials, such as , , and , exhibit suitable band gaps alongside excellent carrier mobility. Their high compatibility with existing silicon-based chip technologies further positions them as suitable channel materials for 2D field-effect transistors (FETs). Using first-principles calculations, we systematically investigate the transport properties of monolayer metal-oxide-semiconductor field-effect transistors (MOSFETs) and benchmark their performance against the International Technology Roadmap for Semiconductors (ITRS) 2028 requirements for high-performance (HP) and low-power applications. These MOSFETs achieve peak on-state currents () of 4157 and 3527 for - and -type HP devices, respectively, with notably low delay times and power dissipation (PDP). They maintain compliance with ITRS 2028 standards when scaled to gate lengths as small as 3 nm. When scaled to 5 nm, the subthreshold swing reaches 58 mV/dec, surpassing the Boltzmann thermal limit of 60 mV/dec. Compared to other 2D materials, MOSFETs deliver higher , lower , and reduced PDP, establishing them as highly promising candidates for next-generation 2D FET applications.