Cryogenic temperature dependence and hysteresis of surface-trap-induced gate leakage in high-electron-mobility transistors
Phys. Rev. Applied 24, 044018 – Published 7 October, 2025
DOI: https://doi.org/10.1103/ngfc-3xr1
Abstract
This work provides a detailed mapping of various mechanisms of surface-trap-induced gate leakage in HEMTs across a temperature range from room to cryogenic levels. Two-dimensional variable-range hopping is observed at small gate bias. Under higher reverse gate bias, the leakage is dominated by the Poole-Frenkel emission above 220 K, but gradually transitions to the trap-assisted tunneling below 220 K owing to the frozen-trap effect. The trap barrier height extracted from the gate leakage current under the upward gate sweep is 0.65 V, which is 12% higher than that from the downward sweep. The gate leakage current as a function of the gate bias exhibits clockwise hysteresis loops above 220 K but counterclockwise ones below 220 K. This remarkable opposite hysteresis phenomenon is thoroughly explained by the trap mechanisms.
