The semiconductor chip manufacturing process is complex and lengthy, and potential errors can arise at every stage. Each wafer contains numerous chips, and wafer bin maps can be generated after chip testing. By analyzing the defect patterns on these wafer bin maps, the manufacturing steps at which errors occur can be inferred. In this work, we improve the quantum Bayesian inference algorithm and apply the proposed algorithm to accelerate the identification of error patterns on wafer bin maps, thereby assisting in chip yield analysis. We show the algorithm for error identification and detail the implementation of the improved quantum Bayesian inference. Our results demonstrate the speed advantage of quantum computation over classical algorithms for a real-world problem, highlighting the practical significance of quantum computation for many problems based on Bayesian inference.

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• Bayesian networks
• NP-hard problems
• Quantum algorithms
• Device fabrication
• Semiconductors
• Bayesian methods
• Machine learning