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Reducing the computational cost scaling of tensor network algorithms via field-programmable gate array parallelism

Songtai Lv1, Yang Liang2, Rui Zhu3,4, Qibin Zheng2,*, and Haiyuan Zou1,†

  • *Contact author: qbzheng@usst.edu.cn
  • †Contact author:  hyzou@phy.ecnu.edu.cn
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APS Open Sci. 1, 000064 – Published 16 July, 2026

DOI: https://doi.org/10.1103/ktzw-t6fx

Abstract

Improving the computational efficiency of quantum many-body calculations from a hardware perspective remains a critical challenge. Although field-programmable gate arrays (FPGAs) have recently been exploited to improve the computational scaling of algorithms such as Monte Carlo methods, their application to tensor network algorithms is still at an early stage. In this work, we propose a fine-grained parallel tensor network design based on FPGAs to substantially enhance the computational efficiency of two representative tensor network algorithms: the infinite time-evolving block decimation (iTEBD) and the higher-order tensor renormalization group (HOTRG). By employing a quad-tile partitioning strategy to decompose tensor elements and map them onto hardware circuits, our approach effectively translates algorithmic computational complexity into scalable hardware resource utilization, enabling an extremely high degree of parallelism on FPGAs. Compared with conventional CPU-based implementations, our scheme exhibits superior scalability in computation time, reducing the bond-dimension scaling of the computational cost from O(Db3) to O(Db) for iTEBD and from O(Db6) to O(Db2) for HOTRG. This work provides a theoretical foundation for future hardware implementations of large-scale tensor network computations.

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APS Open Sci. 1, 000064– Published 16 July, 2026
Vol. 1
  • Received 11 February 2026
  • Revised 6 June 2026
  • Accepted 15 June 2026
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