Manipulating Transistor Operation via Nonuniformly Distributed Charges in a Polymer Insulating Electret Layer

Organic field-effect transistors (FETs) with high-field-effect mobility (${\mu }_{\mathrm{FET}}$) and on:off ratio are attractive for flexible electronics. In this paper, we propose a design principle for manipulating transistor operations to in situ improve both the ${\mu }_{\mathrm{FET}}$ and on:off ratio of polymer transistors using nonuniformly distributed charges along an insulator electret layer between semiconductor and dielectric layers. Such nonuniform electrets obtained via applying gate-voltage stress with specific source-drain voltages provide a nonuniform electric field across the semiconductor layer and, thus, serve as a “nonuniform floating gate”. As compared with transistors without electrets or with uniform electrets, nonuniform electrets lead to a different device operation; therefore, a much narrower gate-voltage range can be sufficient to switch the transistor between the on and off states representing a higher switching speed. The apparent ${\mu }_{\mathrm{FET}}$ of poly(3-hexylthiophene) semiconductor film is significantly improved by 1 order to higher than $1{\mathrm{cm}}^2{\mathrm{V}}^{-1}{\mathrm{s}}^{-1}$, with simultaneously improving the on:off ratio up to ${10}^8$.

Figure 1

Tuning the performance of the field-effect transistor upon manipulating charge distribution in the insulator electret. (a) Scheme of the transistor based on P3HT:PS blends where the PS layer acts as an insulator electret. (b) Measured apparent ${\mu }_{\mathrm{FET}}$ of the transistors with different charge distribution within the PS electret. (c) One-step stress. Dependence of $I_{SD}$ ($V_D=-100\mathrm{V}$) on $V_G$ while applying a variable gate-voltage stress ($V_G$ scanned from 20 to $-80\mathrm{V}$) at $130°\mathrm{C}$. (d) Two-step stress. Dependence of $I_{SD}$ ($V_D=-100\mathrm{V}$) on variable gate-voltage stress (the second step $V_G$ is scanned from 20 to $-80\mathrm{V}$) at $20°\mathrm{C}$ after the device is prestressed (the first step) under condition ($V_G=-100\mathrm{V}$, $V_S=V_D=0\mathrm{V}$, $130°\mathrm{C}$). The lines in (c) and (d) are guides. The pink curves in (c) and (d) are the transfer curves measured at room temperature (no charge injected into PS) without gate-voltage stress. The insets of (c) and (d) are schemes for the density profile of immobilized charges within PS, where $S$ and $D$ represent the source and drain electrodes, respectively, and $M$ is the critical point where charge starts being injected from P3HT into PS. Higher $-V_G$ increases the charge density in the PS electret near the source electrode and shifts the profile from the solid line towards the dashed line.

Figure 2

In situ manipulation of the transistor operations upon one-step stress at $130°\mathrm{C}$. (a) Transfer characteristics before and after one-step gate-voltage stress. See Fig. 1 for the gate stress at $130°\mathrm{C}$. (b) Dependence of ${I_{SD}}^{0.5}$ on $V_G$ before and after gate stress. (c) Dependence of apparent field-effect mobility on $V_G$ before and after gate stress. (d) After gate stress, the device operation is stable upon repeated scanning, showing that the nonuniform charge is stably trapped within the PS electret.

Figure 3

Manipulation of transistor operations upon applying a two-step stress. The transistor is prestressed (the first step) under condition ($V_S=V_D=0\mathrm{V}$, $130°\mathrm{C}$) with different prestress $V_G$ and then poststressed (the second step) by scanning $V_G$ from 20 to $-80\mathrm{V}$ [see Fig. 1] with $V_D$ simultaneously kept at $-100\mathrm{V}$. (a) Dependence of ${I_{SD}}^{0.5}$ on $V_G$ for different prestress gate voltages. The device is poststressed using the same process. (b) Dependence of apparent ${\mu }_{\mathrm{FET}}$ on $V_G$ as obtained from (a). Transfer (c) and output (d) characteristics of a transistor treated by the two-step stress (prestress $V_G=80\mathrm{V}$).

Figure 4

(a) Dependence of transfer characteristics (${I_{SD}}^{0.5}$ vs $V_G$) on the temperature for a transistor with a nonuniform electret. The inset is $I_{SD}$ vs $V_G$ in logarithmic scale. (b) Activation energy $E_a$ extracted from the dependence of ${\mu }_{\mathrm{FET}}$ on the temperature via the Arrhenius equation. The line is a guide for the eyes.

Figure 5

Numerical simulation for transistors with the nonuniform electret using the simplified model described by Eqs. (3)–(5). (a) Areal charge distribution in the PS electret tentaviely assumed, which is according to the experimental observations in Figs. 1 and 1. The transistor is treated by the two-step stress including a prestress [$V_G$ is shown in (a), $V_S=V_D=0\mathrm{V}$, $130°\mathrm{C}$] and a post-stress [$V_G$ scanned from 20 to $-80\mathrm{V}$, $V_D=-100\mathrm{V}$, $20°\mathrm{C}$; see Fig. 1]. Simulated $V_M$ in the semiconductor layer at different $V_G$ (b) and simulated dependence of ${I_{SD}}^{0.5}$ on $V_G$ (c) according to charge distribution profiles in (a). (d) Simulated apparent ${\mu }_{\mathrm{FET}}$ from (c). The dashed line is a guide to show that the apparent ${\mu }_{\mathrm{FET}}$ rapidly decays with decreased $-V_G$. Prestress $V_G=0\mathrm{V}$ represents no gate stress in the first step. Inset is the hole density $P$ (prestress $V_G$ is 60 V) in the semiconductor layer at different postions in the channel.

Figure 6

Simulation using both the dependence of the carrier mobility on the charge density $\mu (P)$ in the semiconductor and the charge distribution profile $Q(l)$ in the insulator electret. (a) Dependence of the mobility on the areal charge density in the semiconductor layer, which is measured in transistors without the electret. (b) Simulated dependence of ${I_{SD}}^{0.5}$ on $V_G$ according to the charge distribution profiles as shown in Fig. 5. (c) Simulated apparent ${\mu }_{\mathrm{FET}}$ from (b).