Increasing the utility of currently available noisy intermediate-scale quantum (NISQ) devices requires developing efficient methods to mitigate hardware errors. In this work we propose a novel cyclic layout permutations based zero noise extrapolation (CLP-ZNE) protocol for such a task. The method leverages the inherent nonuniformity of gate errors in NISQ hardware to extrapolate the expectation value, averaged over cyclic circuit layout permutations, to the level of zero noise. In contrast to the previous layout permutation based approaches, for $n$-qubit circuit CLP-ZNE requires execution of only $O\left(n\right)$, and at most, $O\left(n^2\right)$ different circuit layouts for circuits of one-dimensional and arbitrary connectivity, respectively. When benchmarked against noise channels modeling the IBM Torino quantum computer, the method reduces a typical error in expectation values of $n=12$ qubit circuits by an order of magnitude, outperforming standard unitary folding ZNE. By demonstrating the ability to mitigate noise of real hardware specifications, including both depolarizing and $T_1/T_2$ relaxation processes, these results give evidence for the applicability of CLP-ZNE to present-day NISQ processors.

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• Quantum algorithms & computation
• Quantum circuits
• Quantum gates